1. Field of the Invention
The present invention relates to a solid-state image sensor and a camera.
2. Description of the Related Art
A solid-state image sensor includes a pixel array in which a plurality of pixels are arranged. Japanese Patent Laid-Open No. 2005-311821 discloses an arrangement in which a plurality of column signal lines are arranged in each column of the pixel array. According to Japanese Patent Laid-Open No. 2005-311821, a plurality of pixel signals can be read out from each column of the pixel array simultaneously, thereby making a high read rate possible.
Along with an increase in pixel density of the solid-state image sensor, a layout technique of a signal wiring, which achieves the high rate while improving light collection efficiency, is required. Japanese Patent Laid-Open No. 2011-82769 discloses an example of a layout technique of a structure in which a plurality of signal wirings are arranged in each column of the pixel array parallelly. For example, FIG. 4 of Japanese Patent Laid-Open No. 2011-82769 discloses a structure in which a first column readout line 106_even and a second column readout line 106_odd are alternately formed adjacent to an output unit (a diffusion region of a row selection transistor 105) for each row of pixels. This can be done with a plurality of wiring layers.
In order to arrange a control line for controlling each pixel in the pixel array, a layout needs to be contrived to form, using a small number of wiring layers, a portion in which the control line, and the first and the second column readout lines intersect.